The present invention generally relates to a multilayer printed circuit board and particularly relates to a multilayer printed circuit board in which an inner layer pattern such as an earthing layer, a power supply layer, or the like, is standardized so that the inner layer pattern can be commonly used even if a pattern of a signal layer is varied.
FIGS. 1 and 2 show the conventional multilayer printed circuit board. In the drawings, the reference numeral 1 designates a multilayer printed circuit board, and the reference numeral 2 designates a signal layer formed as an inner layer and constituted by a plurality of signal lines 2a. The reference numerals 3 and 4 designate terminal insertion holes and terminal insertion lands for mounted parts, which are formed at intersecting points 5c between a first plurality of main reference grid lines 5a and a second plurality of main reference grid lines 5b extending perpendicularly to each other, that is, the main reference grid lines 5a in the first plurality extending in the longitudinal direction while the main reference grid lines 5b in the second plurality extending in the transversal direction. In such an arrangement as described above, for example, in the case where one grid pitch P between the intersecting points 5c is selected to be 2.54 mm, it is possible to make the maximum number n of signal lines 2a in one grid be four, while similarly to this case, in the case where the grid pitch P is selected to be 1.27 mm, it is possible to make the maximum number n of signal lines 2a in one grid be one or two, so that a density of signal lines on a printed substrate can be made high. Thus, in the prior art multilayer printed circuit board, although making high the density of signal lines on the printed substrate has been taken into consideration, in the case where signal lines of signal layers carrying patterns different from each other are connected to each other, only the intersecting points 5c between the main reference grid lines 5a and 5b have been utilized for via holes each exclusively used to connect the signal line thereto. In this case, the number of terminal insertion holes 3 used as part terminal insertion holes has been limited, so that there has been such anxiety that a density of actually mounted parts is reduced. Further, when the via holes each exclusively used to connect the signal line 2a thereto are formed at the intersecting points 5c between the main reference grid lines 5a and 5b, gaps between signal lines 2a are made unequal, so that the insulating characteristic between signal lines 2a is varied depending on the positions of the signal lines 2a, resulting in deterioration in the entire insulating characteristic.
Moreover, generally, in the multilayer printed circuit board, an inner layer pattern such as an earthing layer, a power supply layer, or the like, which is formed by etching copper foil, is sometimes provided as an inner layer. In view of the purpose of provision of the earthing layer or the power supply layer, it is required for the inner layer to carry a pattern continued all over the entire plane of the printed circuit board except portions which are not electrically connected to peripheral portions of the terminal insertion holes 3 (hereinafter, referred to as clearance holes). Further, for example, as a matter of course, the terminal insertion hole used to insert a power supply terminal of an LSI therein is connected to the power supply layer.
In the case where the foregoing via holes are formed in such a multilayer printed circuit board containing the inner layer pattern such as a power supply layer, an earthing layer, or the like, it is a matter of course that the clearance holes must be formed at the peripheral portions of the via hole. On the other hand, it is the real situation that at the most one via hole can be formed in each region sectioned by the main reference grid lines 5a and 5b, as shown in FIG. 1 because of the foregoing requirement for the inner layer pattern (that is, the inner layer pattern must be continued all over the entire plane of the printed circuit substrate). Otherwise, central clearance holes used for a plurality of via holes are communicated with clearance holes used for the terminal insertion holes 3, which are disposed adjacently on both sides thereof, so that the inner layer pattern in which the clearance holes are communicated with each other does not function as the power supply layer or the earthing layer. Further, conventionally, since via holes have been formed only at positions where among a plurality of signal lines 2a respectively extending in the longitudinal and transversal directions, signal lines to be actually connected to the via hole are disposed, inner layer patterns are different from each other for individual printed circuit boards, resulting in increase in designing of the inner layer pattern and/or in manufacturing the boards.
Although there are some prior art references as to the multilayer printed circuit board of this kind, for example, Japanese Utility Model Publication No. 57-52949, Japanese Patent Unexamined Publication No. 55-103793, etc., it has not been taken into consideration at all that the degree of freedom in design of the signal layer is improved by increasing the number of via holes, or that one inner layer pattern is made to be commonly used for various circuit boards by standardizing the inner layer pattern.